1. Field of the Invention
The present invention relates to a method of fabricating a low temperature polysilicon thin film transistor liquid crystal display (LTPS TFT-LCD), and more particularly, to a method of fabricating a LTPS TFT-LCD composed of P-type LTPS TFT by utilizing seven photo-etching processes (PEPs).
2. Description of the Prior Art
Currently, liquid crystal displays (LCDs) represent a commona flat panel display technology. Applications for LCDs are extensive and include mobile phones, digital cameras, video cameras, notebooks, and monitors. Due to high quality display requirements and the expansion of new application fields, the development of LCDs have found on the following criteria: high resolution, high brightness, and low price. Development of LTPS TFTs, being actively driven, has been a break-through in achieving the above objectives. Therefore, technological innovation based on the LTPS TFT concept has become an important subject for further development.
Please refer to FIG. 1 to FIG. 8. FIG. 1 to FIG. 8 are schematic diagrams of a method for forming a LTPS TFT-LCD according to a prior art. The prior art LTPS TFT-LCD 98 is formed on an insulation substrate 10. The insulation substrate 10, composed of transparent materials, may be a glass substrate or a quartz substrate. A pixel array area 11 and a periphery circuit area 13 are formed on a surface of the insulation substrate 10.
As shown in FIG. 1, an amorphous silicon (α-Si) thin film (not shown) is first formed on the surface of the insulation substrate 10. Then, an excimer laser annealing (ELA) process is performed to re-crystallize the amorphous silicon thin film into a polysilicon layer (not shown). A first photo-etching processes (PEP-1) is thereafter performed to define an active area 12 in the pixel array area 11 and at least one active area 14 in the periphery circuit area 13. A source region (not shown), a drain region (not shown), a channel region (not shown), and a predetermined region for a bottom storage electrode (not shown) are formed in the active area 12; a source region (not shown), a drain region (not shown), and a channel region (not shown) are formed in each active area 14.
As shown in FIG. 2, a second photo-etching process (PEP-2) is performed to form a photoresist layer 16 on the top surface of the insulation substrate 10. The photoresist layer 16 is used to define the location for the bottom storage electrode 18 in the pixel array area 11. After that, an ion implantation process is performed to add high concentration N-type dopants into the exposed portion of the active area 12 in the pixel array area 11, completing the fabrication of the bottom storage electrode 18.
The photoresist layer 16 is removed. As shown in FIG. 3, an isolation layer 22 and a first conductive layer (not shown) are formed on a surface of the entire structure sequentially. Then a third photo-etching process (PEP-3) is performed to simultaneously form a gate electrode 24 of a TFT, a top storage electrode 26 on the bottom storage electrode 18 in the pixel array area 11, a gate electrode 28 of an NMOS and a gate electrode 32 of a PMOS in the periphery circuit area 13.
As shown in FIG. 4, an etching process is performed, by utilizing the gate electrodes 24, 28, 32, and the top storage electrode 26 as etching masks, to remove portions of the isolation layer 22 to form the gate insulating layers 34, 36, 38, and the capacitor dielectric layer 42. The manufacturing of the storage capacitor 44 is thus completed.
After that, an ion implantation process, by utilizing the gate electrodes 24, 28, 32 as masks, is performed to dope low concentration N-type ions into the active areas 12, 14 at either side of the gate electrodes 24, 28, 32 to form lightly doped drains (LDDs) 46, 48, 52. Due to the low concentration N-type ions implanted in this ion implantation process, the doping concentration of the bottom storage electrode 18 is not affected.
As shown in FIG. 5, a fourth photo-etching process (PEP-4) is performed to form a photoresist layer 54 on a surface of the entire structure. The photoresist layer 54 covers the gate electrode 24 and the predetermined region for a lightly doped drain 56 in the pixel array area 11 and simultaneously covers the predetermined region for a PMOS in the periphery circuit area 13. An ion implantation process is thereafter performed to dope high concentration N-type ions to form a source electrode 62 and a drain electrode 64 of a TFT 58 in the active area 12 in the pixel array area 11 and simultaneously form a source electrode 68 and a drain electrode 72 of an NMOS 66 in the active area 14 in the periphery circuit area 13.
The photoresist layer 54 is removed. As shown in FIG. 6, a fifth photo-etching process (PEP-5) is performed to form a photoresist layer 74 on a surface of the entire structure. The photoresist layer 74 exposes the predetermined region for the PMOS 76 in the periphery circuit area 13. After that, an ion implantation process is performed to dope high concentration P-type ions to form a source electrode 78 and a drain electrode 82 of the PMOS 76 in the active area 14 in the periphery circuit area 13. Due to the high concentration P-type ions implanted in this ion implantation process, the previously formed N-type lightly doped drain 52 (shown in FIG. 5) is compensated and the source electrode 78 and the drain electrode 82 are thus formed.
The photoresist layer 74 is then removed. As shown in FIG. 7, an isolation layer 84 is formed on a surface of the entire structure. The isolation layer 84 covers the gate electrodes 24, 28, 32 and the top storage electrode 26. Then a sixth photo-etching process (PEP-6) is performed to remove portions of the isolation layer 84 to form a plurality of contact holes 85. The contact holes 85 are electrically connected to the source electrodes 62, 68, 78 and the drain electrodes 72, 82, respectively. A source wire 86, electrically connected to the source electrode 62, is formed on top of the isolation layer 84 in the pixel array area 11. Source wires 88, electrically connected to the source electrodes 68, 78 respectively, are formed on top of the isolation layer 84 in the periphery circuit area 13. A wire 92 electrically connecting the NMOS 66 to the PMOS 76 is formed to complete the manufacturing of the CMOS.
As shown in FIG. 8, an isolation layer 94 is formed on a surface of the entire structure to cover the isolation layer 84, the source wires 86, 88, and the wire 92. A seventh photo-etching process (PEP-7) is performed to remove portions of the isolation layer 94 to form a contact hole 95. The contact hole 95 extends downward and is electrically connected to the drain electrode 64. A transparent conductive layer is thereafter formed on the isolation layer 94. Finally, an eighth photo-etching process (PEP-8) is performed to remove portions of the transparent conductive layer to form a pixel electrode 96 on the isolation layer 94. The pixel electrode 96 is electrically connected to the drain electrode 64 downward though the contact hole 95 filled with the transparent conductive layer (not shown) to complete the fabrication of the LTPS TFT-LCD 98.
However, the prior art method for forming the LTPS TFT-LCD results in a very severe problem. When forming the bottom storage electrode, the source electrode, the drain electrode, and the lightly doped drain electorde, three different photoresist layers and four different ion implantation processes required. When forming each photoresist layer, a photolithography process that tends to cause alignment error is required. After so many and complicated photolithography processes, defects are unavoidable in the product. Specifically, the alignment errors incurred from forming the gate electrode and the alignment errors incurred from forming the source electrode and the drain electrode of the thin film transistor in the pixel array area often result in the lightly doped drain having an uneven width. The asymmetric lightly doped drain cannot inhibit the hot electron effect. Moreover, an early breakdown of the device is likely to happen.
Furthermore, the prior art method for forming the LTPS TFT-LCD, following the integrated circuits industry, integrates CMOS. However, with both the NMOS and the PMOS in the circuits, it is impossible to decrease the number of photolithography and ion implantation processes. In addition, the magnitude of the leakage current of the N-type LTPS TFT is difficult to control, resulting in problems in image quality when the N-type LTPS TFT is used in the pixel array area. Therefore, it is very important to develop a method of forming a LTPS TFT-LCD having reduced manufacturing complexity and fewer photolithography processes to lower the probability of misalignment, improve the device defect problem, and improve production yield and image quality.